In semiconductor manufacturing, the complexity of devices formed on semiconductor substrates continues to increase at a rapid pace, while the size of features, such as transistor gates, continues to decrease well below the 93 nanometer (nm) technology node. As a result, manufacturing processes require increasingly sophisticated unit process and process integration schemes, as well as process and hardware control strategies to ensure the uniform fabrication of devices across the substrate. For example, during the fabrication of a gate electrode structure in a transistor device, patterning systems and etching systems, which facilitate the formation of the gate structure in a plurality of material films formed on the substrate, are required to achieve and preserve the gate structure critical dimension (CD) vertically within the device being fabricated as well as laterally across the substrate from device-to-device. A reduction of variations in the CD, as well as variations in profile and side-wall angle (SWA), across the substrate can affect the uniform yield of high performance devices (i.e., speed, power consumption, etc.).
In material processing methodologies, patterning and etching systems are utilized to perform pattern etching, which comprises applying a thin layer of radiation-sensitive material, such as photoresist, to an upper surface of a substrate, patterning this thin layer of radiation-sensitive material using photolithography to form a pattern therein, and transferring the pattern to the underlying material film using an etching process. For example, the patterning of the radiation-sensitive material generally involves coating an upper surface of the substrate with a thin film of radiation-sensitive material (e.g., “photo-resist”), and then exposing the radiation-sensitive material to a geometric pattern of electromagnetic (EM) radiation using, for example, a photolithography system, followed by the removal of the irradiated regions of the radiation-sensitive material (as in the case of positive photo-resist), or non-irradiated regions (as in the case of negative photo-resist) using a developing solvent. Thereafter, the pattern formed in the thin film of radiation-sensitive material is transferred to the underlying layers using an etching process, such as a dry plasma etching process.
During a dry plasma etching process, plasma and the chemistry formed in the presence of plasma are utilized to remove or etch material along fine lines or within vias or contacts patterned on a substrate. The plasma etch process generally involves positioning a semiconductor substrate with an overlying patterned, protective layer, for example a photoresist layer as described above, in a processing chamber. Once the substrate is positioned within the chamber, an ionizable, dissociative gas mixture is introduced within the chamber at a pre-specified flow rate, while a vacuum pump is adjusted to achieve an ambient process pressure. Thereafter, plasma is formed when a fraction of the gas species present are ionized by electrons heated in the presence of an alternating electric field which is created via the transfer of radio frequency (RF) power either inductively or capacitively, or microwave power using, for example, electron cyclotron resonance (ECR). Moreover, the heated electrons serve to dissociate some species of the ambient gas species and create reactant specie(s) suitable for the exposed surface etch chemistry. Once plasma is formed, selected surfaces of the substrate are etched by the plasma. The process is adjusted to achieve appropriate conditions, including an appropriate concentration of desirable reactant and ion populations to etch various features (e.g., trenches, vias, contacts, etc.) in the selected regions of the substrate. Such substrate materials where etching is required include silicon dioxide (SiO2), low-k dielectric materials, poly-silicon, and silicon nitride.
In these plasma etching systems, the uniformity of process results across the substrate are affected by spatial variations in plasma density within the process space above the substrate, typically expressed as a spatial distribution of electron density ne(r,θ), spatial variations in process chemistry (i.e., spatial distribution of chemical species), and spatial variations of the substrate temperature. Often times, the residence time τ(r,θ) of chemical species in the process space may be correlated with the amount of plasma dissociation occurring due to interactions between chemical constituents and energetic electrons and, hence, the residence time may be correlated with process chemistry; i.e., the greater the residence time, the greater the amount of dissociation of chemical constituents and the lesser the residence time, the lesser the dissociation of chemical constituents.
During an etching process, the uniformity of process results can include the uniformity (or non-uniformity) of the spatial distribution of a feature critical dimension (CD) across the substrate or a side-wall angle (SWA) across the substrate. For example, during gate structure formation, it is desirable to achieve a uniform distribution of the gate width (at the top and bottom of the etched feature, as well as the region therebetween) across the substrate following an etching process or series of etching processes.
Since improving process uniformity in semiconductor manufacturing has always been an important goal, there remains a need for systems that improve process parameter uniformity across the surfaces of substrates during processing.